Welcome to Loïc Cudennec Website

  • Kalray MPPA-256 Many-core Processor
  • Intel Itanium Processor
  • Tera 100 / TGCC / Curie


I am a Research Engineer at CEA, LIST in High-Performance and Embedded Computing.

I received both Engineering Degree and Master Thesis in 2005 at INSA de Rennes. I defended my Ph.D. Thesis at the University of Rennes 1, co-funded by the INRIA Centre Bretagne Atlantique, Sun Microsystems and the Regional council of Brittany.

My current works deal with data management over mixed shared and distributed memories architectures in massively parallel processors. In the former CEA-Kalray joint laboratory, I was part of the design and implementation of several steps of the Sigma-C compilation toolchain, as well as its integration process. This toolchain has been transferred to Kalray and is now featured with the MPPA development environment. Some previous works include data consistency management, application planning and deployment over large computing grid architectures.

With Stephane Louise (CEA), we organize the Alchemy Workshop, held in conjunction with the ICCS Conference, to present recent works on many-core architectures. We also organize the GIM2P Session, a special session at the MCSoC Conference.